Fig. 4: ZnO TFT modeling and simulation. | Nature Communications

Fig. 4: ZnO TFT modeling and simulation.

From: CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

Fig. 4

a, b Extracted statistical characteristics of threshold voltage and mobility from 21 fabricated ZnO TFTs, with the Gaussian fit curves. c, d Excellent agreement between the simulation and experimental results for transfer curves and output curves, with an inset in the plot showing the behavior of a fit for just one curve (both log scale and linear scale).

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