Fig. 2
Carrier transport properties of Si nanomeshes. a Schematic of a Si nanomesh transistor. The device is fabricated on an SOI wafer with 100-nm-thick Ni as the source-drain contact, a 120-nm-thick buried SiO2 layer as the dielectric, and Si handle wafer as the global back gate. b Transfer characteristics of the Si-nanomesh transistor with 52.3% fill factor on a log scale (left y-axis) and a linear scale (right y-axis) at a drain voltage of 0.1 V. The channel width and length are 35μm and 40μm, respectively. The inset is the optical image of the as-fabricated device. The scale bar is 20 μm. c Output characteristics of the same device shown in b at gate voltage steps from −2 V (bottom) to 2 V (top). d Extracted effective mobility from transistors of nanomeshes with different Si fill factors as a function of gate voltage
