Extended Data Fig. 8: Two-input logic-in-memory concept and interpretation. | Nature

Extended Data Fig. 8: Two-input logic-in-memory concept and interpretation.

From: Logic-in-memory based on an atomically thin semiconductor

Extended Data Fig. 8

a, Two-input schematic of the logic-in-memory concept. b, Interface model for input polarity control. c, NAND gate, Q1–4 = 2211; d, NOR gate, Q1–4 = 2332; e, XOR gate, Q1–4 = 2222. We derive the XOR canonical form by applying De Morgan’s laws.

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