Fig. 4: Interleaved two-qubit benchmarking and error trends. | Nature

Fig. 4: Interleaved two-qubit benchmarking and error trends.

From: Universal logic with encoded spin qubits in silicon

Fig. 4

a–c, Benchmarking of FW-CNOT (a), SWAP (b) and LCCZ (c) at B = 0 mT, with inset exchange pulse diagrams. Here tidle = 20 ns for FW-CNOT and LCCZ, but tidle = 10 ns for SWAP; tpulse = 10 ns for all. Note, the number of Cliffords excludes the final inverting Clifford. d, Error as a function of gate duration for selected gates (black) (Methods), for various interleaved idle periods (purple) and for two-qubit Cliffords (blue). Idle error increases with gate duration, closely following a theoretical estimate given by (tidle/T2*)2 (purple curve). Some gates show a significant deviation below this curve, indicating that they have some built-in magnetic noise insensitivity. e, Average two-qubit Clifford gate error as a function of B and pulse idle time. B is oriented in-plane and perpendicular to the dot array. We see consistent improvement for lower tidle, eventually limited by the available bandwidth of the signal chain (not shown). As B increases, we first observe an improvement in fidelity above 200  μT, consistent with the suppression of transverse hyperfine magnetic gradients. The fidelity decreases for B > 3 mT because of induced paramagnetic gradients32, see Extended Data Fig. 4. All dots in (a–c) represent the average from 1,000 shots of a single random Clifford sequence. All error bars in this figure correspond to 1σ standard deviation intervals.

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