Fig. 3: Memory performance of the sub-1-ns flash memory.
From: Subnanosecond flash memory enabled by 2D-enhanced hot-carrier injection
a, Schematic diagram of the configuration of the GSG probes in conjunction with the flash device. Inset: a charge-trapping flash structure consisting of a control gate, a memory stack of hBN/HfO2/Al2O3 and the graphene channel. b, Transmission electron microscopy image and elemental mapping image of the sub-1-ns flash device. The thicknesses of Al2O3, HfO2, hBN and graphene are 20 nm, 5 nm, 6 nm and bilayer, respectively. Scale bar, 5 nm. c, The 400-ps programming performance of the device. The test was repeated three times (black and grey curves represent the original state; red and light red curves represent the programmed state). The transfer curves show a large memory window achieved by VD,PROG = −5 V, 400 ps with the grounded gate and source. Inset: the 400-ps program voltage waveform. d, Modulation of Vth through varying program pulse widths at VD,PROG = −5 V with the grounded gate and source. The black and red curves represent a typical original and programmed state, respectively. e, Data retention of the graphene flash memory. The device was measured at room temperature and programmed by VG,PROG = 3.5 V, VD,PROG = −6.8 V (for electron trapping) and VG,PROG = −1.8 V, VD,PROG = 6.6 V (for hole trapping), 800 ps, with source grounding. f, Endurance test of the device. The device was programmed using VG,PROG = VD,PROG = 4.76 V, 20 ns, and VG,PROG = VD,PROG = −4.4 V, 20 ns, respectively, with source grounding.
