Extended Data Fig. 2: Schematic structure of the FPGA board and its program. | Nature Neuroscience

Extended Data Fig. 2: Schematic structure of the FPGA board and its program.

From: Real-time analysis of large-scale neuronal imaging enables closed-loop investigation of neural dynamics

Extended Data Fig. 2

a, The FPGA board consists of modules for image acquisition and pre-processing. The image acquisition daughterboard is connected via the FMC HPC connector. The received image data are cached at the QDRII, with a current capacity of 18 MB. The system utilizes a ping-pong buffering mechanism, where two consecutive frames are processed at each time. Therefore, the cache capacity must be equal to or larger than the size of two frames, which amounts to 16 MB. The image data is then transmitted out through the two QSFP connectors via 10 Gigabit Ethernet. The GPIO (General Purpose Input/Output) is used for serial communication. The QSPI FLASH stores the FPGA configuration memory file. All the modules involved in image acquisition and pre-processing are highlighted in red. b, The FPGA board program includes specific modules for serial port communication and data acquisition. The serial port module receives serial data from host PC and forwards it to the sCMOS through an FMC connector. The data acquisition module parses image data stream obtained with the CameraLink protocol. The data cache module buffers the image data stream and assembles images from it. Finally, the data forwarding module splits the images into two and forwards them as separate streams.

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