Figure 4 | Scientific Reports

Figure 4

From: Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

Figure 4

Switching of memory cell (2,2). (a) Schematic of the measurement circuitry on a representative cell (1,1) in the array (other cells not shown). (b) Input current (top) and sample voltage (bottom) traces of column and row channel (CH) and gate (G). Blue trace (bottom) shows the variation of the MTJ voltage ΔVMTJ. (c) Column bias and enlarged ΔVMTJ show the MTJ state’s responding to the sign of the column bias.

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