Fig. 2
From: Self-selective van der Waals heterostructures for large scale memory array
Memory integration of self-selective memory cells. a Schematic picture of a reading process using a one-half voltage scheme. The selected memory cell with a net voltage application of ‘V’ is highlighted in pink, while either one-half ‘V’ or zero voltage bias is applied to the other memory cells. b Reliability of the three states: the low-resistance state (probed by Vread), high-resistance state (probed by Vread), and unselected state (probed by one-half Vread) exhibit narrow voltage windows and a high selectivity of larger than 1010 in the cumulative probability of resistances. c Readout margin for three different wire resistances between neighboring cells simulated by using SPICE modeling. A 1/2 V voltage scheme was used in the simulation, while a 1/3 V voltage scheme showed a similar result (Supplementary Fig. 11). d Simulated capacity-dependent energy efficiency with three different wire resistances. An energy efficiency of 10% was observed at an integration capacity of one terabit by SPICE modeling, which is consistent with the greatly suppressed sneak current due to the high selectivity of larger than 1010 in (b). The unit wire resistance calculated in our work is less than 10 Ω (see Methods). Thus, the maximum wire resistance used for this simulation is 10 Ω
