Fig. 1: Vertical lamination processes and characterization of MoS2 based vertical sidewall transistors.
From: High-density vertical sidewall MoS2 transistors through T-shape vertical lamination
a–e Schematics and the corresponding optical images of the vertical lamination processes with 5 steps: planar MoS2 transistors pre-fabricated on a sacrificial substrate (a), fabrication of vertical silicon trench through etching (b), dry-transfer of MoS2 transistors with the polymethyl methacrylate (PMMA) gap on top of Si trench (c), T-shape polydimethylsiloxane (PDMS) stamp laminated and pushed into the trench (d), and MoS2 vertical transistors after lamination (e). f Scanning electron microscopy (SEM) image of the fabricated MoS2 vertical transistors on vertical substrate. g–i Cross-sectional SEM image (g) and scanning transmission electron microscopy (STEM) images (h, i) of the vertical transistors, indicating the optimized interface after vertical lamination. Scale bars are 10 μm for panel a, c, e, 20 μm for panel b, d. S, source; D, drain.
