Fig. 1: 3D integrated Si PIC chip.

a, Left: concept of 3D photonic integration of functional layers (top) and the corresponding devices on a fabricated 3D PIC (device picture shown in the bottom). This chip is singulated from a fully fabricated 100-mm-diameter wafer. The SiN wafer process is performed on a 200-mm-diameter wafer fabricated in a CMOS foundry, which was later cored into 100-mm-diameter wafers for heterogeneous laser fabrication. Right: the cross-section of the demonstrated 3D PIC in solid colours. We envision that future works will enable additional functionality, such as integration with foundry-available Si modulators and Ge/Si PDs, and 3D electronic–photonic heterogeneous integration, which are shown in transparent colours. Both monolithic and heterogeneous integration processes are employed, in which 3D transitions are critical to the vertical integration of functionality layers. b, Measured III–V/Si DFB laser spectrum centred at the telecom C band on the 3D PIC (right axis) and measured ULL SiN waveguide loss (left axis, extracted from the fitted resonator Q) across the telecom S, C and L bands on the same 3D PIC. c, Left: false-coloured focused ion beam scanning electron microscopy image of the fabricated 3D PIC showing the laser cross-section. Right: transmission electron microscopy image showing the layered InP epitaxial stack after bonding and substrate removal.