Abstract
Federated learning provides a framework for multiple participants to collectively train a neural network while maintaining data privacy, and is commonly achieved through homomorphic encryption. However, implementation of this approach at a local edge requires key generation, error polynomial generation and extensive computation, resulting in substantial time and energy consumption. Here, we report a memristor compute-in-memory chip architecture with an in situ physical unclonable function for key generation and an in situ true random number generator for error polynomial generation. Our architecture—which includes a competing-forming array operation method, a compute-in-memory based entropy extraction circuit design and a redundant residue number system-based encoding scheme—allows low error-rate computation, the physical unclonable function and the true random number generator to be implemented within the same memristor array and peripheral circuits. To illustrate the functionality of this memristor-based federated learning, we conduct a case study in which four participants cotrain a two-layered long short-term memory network with 482 weights for sepsis prediction. The test accuracy on the 128-kb memristor array is only 0.12% lower than that achieved with software centralized learning. Our approach also exhibits reduced energy and time consumption compared with conventional digital federated learning.
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Data availability
The datasets that we used for benchmark are publicly available. The source data of Figs. 2c–e, 3f–h and 4c–f, Extended Data Figs. 2c–g and 3 and Supplementary Figs. 1, 2 and 4 are available via GitHub at https://github.com/Tsinghua-LEMON-Lab/Memeristor_based_Federated_Learning. Source data are provided with this paper. Additional data supporting the findings of this study are available from the corresponding authors upon reasonable request.
Code availability
The codes that support the findings of this study are available via GitHub at https://github.com/Tsinghua-LEMON-Lab/Memeristor_based_Federated_Learning. Additional codes are available from the corresponding authors upon reasonable request.
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Acknowledgements
This work is supported in part by the STI 2030-Major Projects (grant no. 2021ZD0201200, H.W.), the National Natural Science Foundation of China (grant nos. 62495100 to H.W., 62025111 to H.W., 92464302 to B.G. and 624B2078 to X.L.), the Tsinghua IDG/McGovern ‘Brain+X’ Seed Grant Doctoral and Postdoctoral Program (X.L.), the Shanghai Municipal Science and Technology Major Project (H.W.), the Beijing Advanced Innovation Center for Integrated Circuits and the IoT Intelligent Microsystem Center of Tsinghua University-China Mobile Communications Group Co., Ltd Joint Institute.
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X.L. contributed to the overall experiment design and the writing of the paper. B.G., J.T., X.Y., H.Q. and H.W. contributed to the memristor fabrication process development. Q.Q., P.Y. and Z.H. designed the memristor circuits and built the test board. P.Y., J.L. and C.L. contributed to the benchmark of the system performance. Z.H. and J.X. helped with data analysis. Q.Z., Y.L., D.K., J.Y. and Y.N. worked on the finding of demonstration scenes and the development of AI models. B.G., X.Y. and H.W. supervised this project. All authors discussed the results and reviewed the paper.
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Nature Electronics thanks Kasem Khalil and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.
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Extended data
Extended Data Fig. 1 The test platform, the chip and the memristor device.
a, Photography of the test board of the 128Kb memristor chip. The test board is mounted on the V93000 test platform for controlling and testing the chip. b, The optical photograph of the 130 nm 128Kb memristors chip. The floorplan of the chip, including the digital control core and the analog crossbar core. c, The floorplan of the analogue crossbar core, including the array, BL/WL/SL drivers, SL read current paths, and BL/WL/SL voltage multiplexers. d, Transmission electron microscope (TEM) image of memristor array. e, Transmission electron microscope (TEM) image of memristor device.
Extended Data Fig. 2 The circuit design of the proposed CIM-based TRNG entropy extraction circuit.
a, The proposed CIM-based TRNG entropy extraction circuit design and working principle. In the CPTIN architecture, the same memristor cell serves as both the TRNG entropy source and the CIM computation unit. In CIM, the memristor cell may store a bit value of 1 or 0, which means that its resistance can be quite high or quite low. To adapt to this situation, we have set two charging capacitors, C1 and C2. When the resistance of the memristor is high, we connect a smaller charging capacitor C1; conversely, when the resistance is low, we switch to a larger charging capacitor C2. This ensures that the entropy extraction circuit can generate random numbers regardless of the memristor resistance. The circuit parameters are set as follows: C1 = 7fF, C1 = 500fF, VREAD = 200 mV and VTRNG_REF = 170 mV. b, Formula for calculating the theoretical output value of the TRNG. c-e, The TRNG simulation results for low resistance devices. The read resistance variation (c). The read resistance distribution of 10 randomly selected devices; a normal distribution was fitted to the results of 1000 read cycles, the curves represent the fitted results, and the horizontal line represents the mean of the normal distribution fit. (d). The corresponding TRNG output simulated by Cadence. (e). f-h, The TRNG simulation results for high resistance devices.
Extended Data Fig. 3 Supplementary Figure 7. The reliability of the 4-client federated learning.
In memristor-based federated learning, errors occur during the memristor-based encryption and decryption computations with a computational error rate of \(x\). The error rate of memristor computation leads to an error rate in the weight gradient \(\Delta W\) for weight updating. For an individual user in federated learning, the encryption and decryption computations increase the error rate of \(\Delta W\) to \({1-(1-x)}^{2}\). For a 4-client federated learning process, the total error rate of \(\Delta W\) will theoretically reach \({1-(1-x)}^{8}\). In our experiment, the computational error rate (\(x\)) is measured to be 2.24%, and the theoretical total error rate of \(\Delta W\) is 17.7%. a-f, The simulated network performance under the total error rate of \(\Delta W\). The simulation experiment was repeated 50 times for each test point using different random seeds. In the figure, the red curve indicates the average of the 50 experiment results. The bounds of the box indicate the interquartile range, and the whiskers extend to the maximum and minimum non-outlier values within 1.5 times the interquartile range. MCC, Matthews Correlation Coefficient; ROC, Receiver Operating Characteristic.
Supplementary information
Supplementary Information
Supplementary Notes 1 and 2 and Figs. 1–5.
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Source Data Fig. 2
Source data for Fig. 2c–e.
Source Data Fig. 3
Source data for Fig. 3f–h.
Source Data Fig. 4
Source data for Fig. 4c–f.
Source Data Extended Data Fig. 2
Source data for Extended Data Fig. 2c–g.
Source Data Extended Data Fig. 3
Source data for Extended Data Fig. 3.
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Li, X., Gao, B., Qin, Q. et al. Federated learning using a memristor compute-in-memory chip with in situ physical unclonable function and true random number generator. Nat Electron 8, 518–528 (2025). https://doi.org/10.1038/s41928-025-01390-6
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DOI: https://doi.org/10.1038/s41928-025-01390-6
