Highly passivated TOPCon bottom cells for perovskite/silicon tandem solar cells

Perovskite/silicon tandem solar cells (TSCs) have attracted considerable attention due to their advantages in efficiency and potential fabrication cost. Recent advancements have propelled this type of TSCs to achieve a record efficiency of 33.9%¹. Additionally, the shared module structures with single-junction solar cells facilitate the integration of TSCs into module production without the need for additional scaffolds and wires. Silicon solar cells with the Tunnel Oxide Passivated Contact (TOPCon) structures are rising with the advantages of high power conversion efficiency (>26%)¹ because it has already proven to be an upgrade from existing Passivated Emitter and Rear Contact cell production lines. These advantages make TOPCon cells, even with TOPCon structures on both sides, become a promising candidate as bottom sub-cells for perovskite/silicon TSCs.

In the pursuit of high-efficiency TSCs, texturing the front side of the silicon cell is indispensable as it could significantly reduce the refection of incident photons and extend the propagation length of photons in the absorbers^2,3,4. TOPCon bottom cells contribute lower voltage in TSCs compared to mainly researched silicon heterojunction (SHJ) bottom cells, which could be ascribed to the weak passivation of the textured p-type side. The saturated current density (J_0,s) of the p-type sides in TOPCon cell and SHJ cell is reported as 15.2 fA·cm⁻² and 5.1 fA·cm⁻², respectively^5,6, which may support the correlation of lower p-type side passivation with lower voltage. Although p-type TOPCon structures on planar substrates have exhibited high passivation with implied open-circuit voltage (iV_OC) over 730 mV^7,8,9, the structures on textured counterparts still suffer from a lower passivation quality compared to p-type a-Si:H passivated textured sides in SHJ cells. This is primary due to the higher defect density in and/or near the ultrathin silicon oxide (SiO_x) interlayer, resulting from a higher defect density on textured surface before oxidation, and the formation of degraded SiO_x and boron-based clusters formed during boron in-diffusion¹⁰. The rounding etching process on the textured surface indeed reduces surface defects but simultaneously enhances reflectance^9,11. Therefore, the textured surface is kept intact but an additional Si/SiO_x stack was inserted to reduce boron corrosion on the SiO_x/c-Si interface¹². With a common alumina oxide/silicon nitride (AlO_x/SiN_x) capping layer, the sample showed an iV_OC of 710–720 mV. Further enhancement was achieved with a multilayer hydrogenation stack, effectively suppressing defect density and acquiring an iV_OC above 720 mV. However, the additional insertion and multilayer structure increase complication of production line, leading to higher costs.

In this work, industry-compatible fabrication methods, such as ambient-pressure thermal oxidation and in situ plasma-enhanced chemical vapor deposition (PECVD), are employed to prepare highly passivated p-type TOPCon structures and double-sided TOPCon bottom cells on industrial textured wafers. The use of thermal oxidation avoids damages from ion-bombardment during the high-power plasma oxidation^13,14. Different from successive thermal oxidation and poly-Si deposition in a single tool, ex situ thermal oxidation yields ultrathin SiO_x layers on both wafer sides in an oxidation facility, such as a tube furnace, after which the wafers are transferred to PECVD facility to deposit intrinsic and doped silicon. The oxidation and silicon deposition processes are performed in different facilities. The mass production process technology of TOPCon structures via in situ doped amorphous silicon (a-Si) has been achieved by Feldmann et al. in 2020¹⁵ and Ma et al. in 2023¹⁶. Compared to widely used low pressure CVD, this in situ PECVD technique provides high versatility not only in dopant species and doses, but also in multilayer film structure. Additionally, it boasts a high SiH₄ utilization rate and allows for single-side oxidation or deposition. Furthermore, this technique may avoid the damage of quartz furnaces and carriers caused by wrap-round effect¹⁷. The combination of ex-situ thermal oxidation and in situ doped a-Si is able to achieve single-side TOPCon structures. Chemical and field-effect passivation are significantly promoted through mitigating ultrathin SiO_x distortion by stronger oxidation, enhancing boron in-diffusion by employing a higher thermal budget, and suppressing a higher residual defect density by strengthened hydrogenation. Consequently, the iV_OC of the sample with p-type TOPCon structures on both sides exceeds 715 mV with single-side J_0,s below 13 fA·cm⁻², and the V_OC of completed bottom cells approaches 710 mV. Employing the optimized TOPCon bottom cells, 1 cm² n-i-p monolithic perovskite/silicon TSCs achieve high V_OCs of 1.9 V and a high efficiency of 28.2% (certified 27.3%). We choose n-i-p configuration to align with single-junction silicon bottom cells featuring p–n junctions at the front side. This configuration holds promise for achieving higher efficiency and prioritizing compatibility.

High passivation of p-type TOPCon structure on textured wafers

The inserted sketch in Fig. 1a illustrates the structure of the passivation sample. The wafers were textured to form sub-micrometer-sized random pyramids on both sides, which were capped by p-type poly-Si films to form p-type TOPCon structures. Firstly, ultrathin SiO_x layers on both wafer sides were formed in an oxidation tool using varying process conditions, and then the wafers are transferred to a PECVD tool to deposit intrinsic and doped silicon. After the high temperature annealing under different thermal budgets, the TOPCon structures were hydrogenated by AlO_x:H with increased thickness. This specific pyramid size was employed to meet the requirements of perovskite top cells.

a Effective carrier lifetime curves and (b) illumination intensity-dependent iV_OC curves of control (in black) and target (in red) samples. The insert in (a) is a structure sketch of double-sided p-type TOPCon structure on textured wafers. The promotion of textured p-type TOPCon structure passivation by optimizing processes step by step: (c) extending oxidation time, (d) elevating 30 min annealing temperature, (e) extending 920 °C annealing dwell time, and (f) increasing hydrogenated AlO_x thickness. The solid curves with closed symbols are for iV_OC and hollow columns are for J_0,s. The added values are iV_OCs and corresponding J_0,ss. The “N₂ + O₂” refers to 500 sccm N₂ + 500 sccm O₂.

Full size image

Figure 1a, b displays the effective carrier lifetime (τ_eff) curves over minority carrier density and iV_OC curves under different illumination intensities, respectively. The fabrication processes of the control samples include a 650 °C/5 min oxidation, 920 °C/30 min annealing, as well as a 15 nm AlO_x:H hydrogenation, according to refs. ^9,10,18. The control sample exhibits a τ_eff of 273 μs and a J_0,s of 34.2 fA·cm⁻² at minority carrier densities of 2 × 10¹⁵ and 5 × 10¹⁵cm⁻³, respectively, together with an iV_OC of 689 mV under 1 Sun illumination. This passivation is lower than that of reference published by Larionova. et al. in 2017¹⁰. To provide a clear understanding of the challenges in passivating textured c-Si wafers, these processes were also performed on a double-sided planar wafer, demonstrating a significantly higher passivation with an iV_OC of 716 mV, a J_0,s of 5 fA·cm⁻², and a τ_eff of 1161 μs. These results seem to be state of the art, as shown in Fig. S1 and Table S1.

The optimization of the textured p-type TOPCon structure sample can be summarized in three key aspects: varying thermal oxidation conditions for different ultrathin SiO_x layers, enhancing the thermal budget in high-temperature annealing for deeper boron in-diffusion, and capping thicker AlO_x:H layers for stronger hydrogenation. As depicted in Figs. 1c and S2, a strong oxidation condition results in a relatively high iV_OC of 690–700 mV. On the base of enhanced oxidation condition, the thermal budget of high-temperature annealing was increased. Figures 1d, e and S3 demonstrate that a 9 min oxidation followed by a 940 °C annealing yields a high iV_OC of 706 mV. Further extension of oxidation time had an inferior effect. Afterwards, in the aluminum oxide hydrogenation process, the AlO_x:H layer thickness was increased up to 35 nm to facilitate strong hydrogen injection. We initially experimented with a bilayer hydrogenation stack of AlO_x/SiN_x but found that it had a negligible effect on improving the passivation quality. Therefore, we used a thicker AlO_x:H layer to enhance passivation. As shown in Fig. 1a, b, f, after optimization the passivation level increased apparently, with an iV_OC of 715 mV at 1 Sun illumination and a J_0,s of 12.9 fA·cm⁻² at the minority carrier density of 5 × 10¹⁵cm⁻³. The τ_eff of 788 μs at the minority carrier density of 2 × 10¹⁵cm⁻³ is also largely higher than the control one. After capping with SiN_x, the iV_OC further increased to 716 mV, which is tagged as the pink circle in Fig. S1. This is the state-of-art passivation level of the p-type TOPCon structure on a textured wafer based on ex situ oxidation and in situ doped a-Si. This data is higher than that from Larionova et al.¹⁰, Kale et al.¹⁹, and Mack et al⁹., but lower than the contact with iV_OC 724 mV and J_0,s 8 fA·cm⁻² reported by Stodolny et al¹². These textured p-type TOPCon structures were all based on thermal oxide. The possible reasons for the lower passivation of the former three contacts may be the single-layer SiN_x:H hydrogenation, as well as the lack of full process optimization. In our p-type passivated contacts the p-type poly-Si layers are 30 nm thick, which are hydrogenated by single-layer AlO_x:H. The higher passivation level of the later one may be ascribed to in situ low pressure thermal oxidation, poly-Si/SiO_x/poly-Si/SiO_x/c-Si multilayer structure and multilayer AlO_x/SiN_x/AlO_x for hydrogenation. The insertion of additional SiO_x/poly-Si leads to lower boron concentration and reduced recombination centers in c-Si, and multilayer hydrogenation injects more H into contact structure which passivates more defects at SiO_x/c-Si interface.

Passivation mechanism and characteristics

Firstly, we conduct a comparison of the thicknesses and integration of ultrathin SiO_x layers on planar and textured wafers. For spectroscopic ellipsometry (SE) analysis, polished wafers with (111)-orientation were used to redraw the oxide formation on the inclined plane of the textured surface. Here, we just wanted to compare the SiO_x thicknesses on planar wafers and on inclined facets of textured wafers. Table S2 displays the calculated thickness of SiO_x under diverse oxidation conditions, revealing a gradual increase in SiO_x thickness on the (111) wafer with stronger oxidation. Though the calculated thickness may not be highly accurate, it is enough to show the trend in SiO_x thickness. Furthermore, the transmission electron microscope (TEM) images in Fig. S4b–d depict that for a 5 min oxidation, the SiO_x on textured surface is thinner, less uniform in thickness, and exposes silicon to metal directly at some positions. In contrast, the SiO_x on the planar surface is more uniform in thickness and covers the silicon surface more completely, as shown in Fig. S4a. This observation is in accordance with previous studies^20,21, suggesting that a strong oxidation process may be necessary to form a thicker SiO_x layer with higher uniformity in thickness, providing enhanced protection to the textured silicon surface. The TEM image in Fig. S4f indicates that a 9 min oxidation results in a thicker SiO_x layer than the 5 min oxidated case in Fig. S4c, and it more conformally segregates the wafer surface from the metal Pd. Additional morphology of the 9 min SiO_x on valleys and tips can be found in Fig. S4e–g. The advantages of 9 min SiO_x remain obvious in poly-Si/ SiO_x/Si structures. After high-temperature annealing, the 9 min SiO_x remains more uniform and consecutive than the 5 min one, as shown in Fig. 2a, b. The corresponding energy disperse spectroscopy (EDS) mappings of oxygen indicate that during annealing, oxygen diffuses into the adjacent silicon to passivate dangling bonds, and the 9 min SiO_x results in a more uniform diffusion (Fig. 2c). Briefly, a 5 min SiO_x interlayer becomes thinner and more discontinued and the diffused O eliminates less defects after annealing, which leaves more defects near the silicon base surface and leads to a lower passivation level with iV_OC of 689 mV and J_0,s of 34.2 fA·cm⁻². Meanwhile, a 9 min SiO_x interlayer protects the silicon base from contacting poly-Si directly after annealing, accompanied by more defects passivated by diffused O, yielding a higher iV_OC of 706 mV and a lower J_0,s of 18.6 fA·cm⁻².

TEM images of Pd/poly-Si/SiO_x/c-Si structures on incline facets of textured wafers for (a) control and (b) target samples, and (c) their local EDS images of O distribution.

Full size image

Next, we focus on the chemical state of Si in ultrathin SiO_x, which was checked via X-ray photoelectronic spectroscopy (XPS) on SiO_x formed directly on textured wafers. The deconvoluted Si spectra for various oxidation conditions are exhibited in Fig. 3a–c, which shows the oxidation conditions and the corresponding calculated Si⁴⁺ peak area ratios. Obviously, a higher oxidation temperature, a longer oxidation time, or a higher oxygen ratio leads to a higher Si⁴⁺ peak proportion, such as 22.7%, 32.1%, and 35.4% for 1, 5, and 9 min oxidation, respectively, meaning an increased Si⁴⁺ concentration in SiO_x. Additionally, a stronger oxidation causes the Si⁴⁺ peak to shift to a higher binding energy (BE), as indicated by the arrows. This suggests that the SiO_x layer is more robust after a strong oxidation. Although the SiO_x interlayers will all suffer from distortion and form defects after high temperature annealing due to the stress from silicon to SiO_x^22,23, it can still be deduced that SiO_x generated from strong oxidation exhibits superior homogeneity and a higher Si⁴⁺ content and BE. Consequently, this lends it a heightened resistance against stress, thereby reducing the likelihood of distortion and minimizing defects within the SiO_x layer. This leaves fewer carrier recombination centers near the SiO_x/c-Si interface and thus a higher passivation.

The influence of oxidation temperature (left column), oxidation time (middle column), and oxidation ambient (right column) on (a–c) Si chemical state in SiO_x, (d–f) interface state density at SiO_x/c-Si, and (g–i) boron in-diffusion profile. The “N₂ + O₂” in (c) refers to 500 sccm N₂ + 500 sccm O₂. The inserted sketch in (f) shows sample structure for C–V test. The “J_{0,Auger_calculated}” in (g) represents Auger recombination rate calculated using in-diffusion profiles in c-Si.

Full size image

Subsequently, the fixed charge density (Q_f) and interface state density (D_it) of the SiO_x/c-Si interface was measured and evaluated using 1 MHz capacitance-voltage (C–V) and conductance-voltage (G–V) curves for various oxidation conditions on textured wafers. The Q_f and D_it were calculated using the data obtained from C–V to G–V curves with Eqs. 1 and 2^24,25, respectively:

where C_ox is the high capacitance plateau of the oxide interlayer, Φ_ms is the difference in metal and semiconductor working functions, V_fb is the flat band voltage, A is the area of the metal disk, q is the electron element, G_m,max is the measured highest conductance, ω is the angular frequency, and C_m is the capacitance corresponding to the measured highest conductance. The C–V curves and corresponding D_it values in terms of oxidation conditions are plotted in Fig. 3d–f. With similar C_ox, the C–V curve shifts to a lower voltage position for stronger oxidation, leading to a lower V_fb and thus lower Q_f of the ultrathin SiO_x/AlO_x stack. This suggests that stronger oxidation results in fewer defects at the SiO_x/c-Si interface. The evaluated D_it values may show this trend more directly, with 3.04 × 10¹²cm⁻²·eV⁻¹ for 5 min oxidation (in red line) verses 2.78 × 10¹²cm⁻²·eV⁻¹ for 9 min oxidation (in yellow line) for example. A higher oxidation temperature or O₂ ratio also yields a remarkable decrease in D_it. After high-temperature annealing, as plotted in Fig. 4a, D_it decreases significantly by an order of magnitude, and D_it of the target sample is lower than that of the control one, showing 3 × 10¹¹cm⁻²·eV⁻¹ vs. 5.95 × 10¹¹cm⁻²·eV⁻¹. This suggests that 9 min SiO_x plus 940 °C annealing is effective in eliminating more defects on the textured c-Si surface, yielding a higher chemical passivation effect.

The comparisons of (a) C–V curves, (b) boron in-diffusion profiles, and (c) O-H peaks in AlO_x:H films of control and target samples.

Full size image

In addition to the analysis of the SiO_x layer or SiO_x/c-Si interface, one key property of the TOPCon structure is the dopant in-diffusion profile obtained by electrochemical capacitance-voltage (ECV) measurement. It shows the active dopant concentration at a specific depth, including poly-Si, SiO_x interlayer, and c-Si beneath SiO_x, which helps to study of the field-effect and chemical passivation. Figure 3g–i displays the doping profiles of textured samples with enhanced oxidation strength after 920 °C annealing. All of them exhibit the trend that stronger oxidation results in a lower depth of boron in-diffusion in c-Si, suggesting fewer boron dopants penetrate ultrathin SiO_x. This means less damage to SiO_x, benefiting chemical passivation. Moreover, the corresponding Auger recombination rates (J_{0,Auger_calculated}) can be calculated based on profiles in c-Si below the SiO_x interlayer using the EDNA2 program in PV Lighthouse^26,27. The Auger recombination rate is positively related to the net dopant concentration (N_dop) and excessive carrier density (Δn)^28,29. For the p-type TOPCon structure, the boron diffusion profile means active boron concentration at an increased depth in c-Si beneath the SiO_x interlayer, and Auger recombination involving one electron and two holes. Therefore, the Auger rate at low injection condition in c-Si below SiO_x can be worked out based on the active boron concentration at a specific depth. At high injection condition, the Auger rate in c-Si below SiO_x is dominated by excessive hole density. As a result, an enhanced boron in-diffusion leads to higher boron concentration in c-Si below SiO_x, and thus higher Auger rate after illumination. A shallow dopant in-diffusion may simultaneously reduce J_{0,Auger_calculated}, improving the τ_eff ²⁷. However, the low active boron concentration in c-Si beneath SiO_x may allow more photo-generated electrons to reach the defect-rich SiO_x/c-Si interface, accelerating carrier recombination^30,31,32. At the same time, a lower boron in-diffusion depth may produce a higher contact resistivity, inhibiting the extraction of generated carriers. Therefore, annealing temperature and dwell time were increased based on strengthened oxidation to explore a balance of chemical passivation, field-effect passivation, and contact resistivity. The comparison of boron in-diffusion profiles between control and target samples can be found in Fig. 4b. With low D_it from 9 min SiO_x, 940 °C annealing leads to deeper boron in-diffusion, which may provide high passivation in both chemical and field-effect aspects. Besides, the calculated J_{0,Auger_calculated} increases only slightly by less than 0.1 fA·cm⁻², having a negligible impact on passivation. Briefly, the lack of boron in-diffusion depth after 920 °C annealing forms a weaker field effect passivation, contributing to lower passivation with iV_OC of 689 mV and J_0,s of 34.2 fA·cm⁻² for the control sample. Meanwhile, 940 °C annealing results in deeper boron in-diffusion thus a stronger field effect passivation, which may be a reason for the higher iV_OC of 706 mV and the lower J_0,s of 18.6 fA·cm⁻² for the target sample.

It could be deduced from the evolution of p-type TOPCon structures that hydrogenation after high temperature annealing also plays a crucial role in achieving high-level passivation. Therefore, the thickness of the AlO_x:H layer was increased by performing more cycle numbers during atomic layer deposition (ALD) to provide sufficient H for passivating p-type TOPCon structures on the textured surface. The cross-sectional scanning electron microscopy (SEM) images in Fig. S5 of the c-Si/SiO_x/poly-Si/AlO_x:H stacks confirm that a higher ALD cycle number indeed improves AlO_x:H thickness to ~30 nm on the inclined facet of a pyramid. The AlO_x:H layer on the valley or tip also becomes thicker. This guarantees sufficient passivation effect for different parts of the textured surface. Furthermore, as the Fourier Transform infrared spectroscopy (FTIR) data shown in Fig. 4c, the as-deposited 30 nm-thick AlO_x:H layer possesses a larger O-H bond peak than the 15 nm one, and this peak collapses drastically after annealing, meaning that a large number of hydrogens are released to passivate defects^33,34. Consequently, the 30 nm-thick AlO_x:H layer attributes to achieve the summit passivation.

The V_OC of a c-Si solar cell can be expressed by a single diode equation^35,36,37,38:

where J_L is the illuminated current density, J_0,emitter is the saturated current density of the emitter, J_0,bulk is the saturated current density in the wafer bulk, and J_0,front or J_0,rear is the saturated current density on the front or rear surface. It can be deduced that for a certain temperature, light absorption, c-Si substrate, and p–n junction, a high surface saturated current density, i.e., a high surface carrier recombination rate, will lead to a low V_OC for a TOPCon cell. Referring to Eq. 1, we can evaluate or predict the V_OC of a bottom cell to some extent. Under the assumptions that the incident light intensity, the carrier recombination rate in the wafer bulk, and the n-type TOPCon structure passivation are fixed and independent with p-type side settings, the V_OC, or the whole passivation, of a bottom cell can be mainly determined by the p-type TOPCon structure passivation quality. The parameters are defined as J_L = 35 mA·cm⁻², J_0,bulk = 10 fA·cm⁻², J_{0,n-type contact} = 5 fA·cm⁻², and the test temperature is 300 K. For a p-type TOPCon structure with low passivation, the J_{0,p-type contact} may be 40 fA·cm⁻², which leads to an V_OC of ~703 mV. When J_{0,p-type contact} decreases to 15 fA·cm⁻², the calculated V_OC will reach ~718 mV.

Double-sided TOPCon bottom cells

An n-type TOPCon structure with high passivation and low contact resistivity on textured wafer is indispensable for a high-performance bottom cell. The structure sketch of a double-sided n-type TOPCon structure on textured wafer is inserted in Fig. 5a. To identify a suitable n-type contact, the deposition time of n-type a-Si was tuned from 80 to 400 s, followed by a 940 °C annealing and a 15 nm-thick AlO_x:H hydrogenation. As displayed in Fig. 5a, b, sample with a deposition time of 320 s yields an iV_OC of 737 mV and a J_0,s of 5.7 fA·cm⁻². With the optimized 30 nm-thick AlO_x:H hydrogenation, the iV_OC and J_0,s of the n-type TOPCon structure passivation sample reach 746 mV and 3.4 fA·cm⁻², respectively.

a The iV_OC and J_0,s of n-type TOPCon structures with different a-Si deposition times on industrially textured wafers. The insert is the structure sketch of double-sided n-type TOPCon structure on textured wafers. b Illumination intensity-dependent iV_OC curves of 320 s n-type TOPCon structures hydrogenated by 15 nm (in black) and 30 nm (in red) AlO_x:H. The corresponding passivation parameters are inserted. c The I–V curves for the target p-type (in green) and n-type (in orange) TOPCon structures for the complete bottom cell. The insert is the schematic structure of a complete n-i-p type double-sided TOPCon bottom cell with sub-micrometer-sized pyramids on the front side and industrial micrometer pyramids on the rear side, respectively. d The J–V curves and corresponding data of control and target complete bottom cells.

Full size image

The low J_0,s of an n-type TOPCon structure together with a highly passivated p-type TOPCon structure contribute to the high iV_OC of 728 mV of the hydrogenated bottom cell. The insert in Fig. 5c depicts the structure sketch of a complete n-i-p type double-sided TOPCon bottom cell. The front side features a control or target p-type TOPCon structure on a sub-micrometer-sized pyramid textured surface, capped by a thick indium tin oxide (ITO) layer and a grid metal electrode for carrier lateral collection. The rear side incorporates an n-type TOPCon structure on a micrometer-sized pyramid textured surface, capped by a full area metal electrode. Figure 5c plots the current-voltage (I–V) curves of the optimized p- and n-type TOPCon structures measured using Cox-Strack method³⁹. The straight curves mean that both TOPCon structures show ohmic contacts, and the p- and n-type TOPCon structures offer contact resistivities of 46 and 40 mΩ·cm², respectively. For comparison, the contact resistivities of p- and n-type TOPCon structures for control bottom cells were also measured using the same method, which are 127 and 332 mΩ·cm², respectively. As a result, the complete bottom cells with control and target TOPCon structures exhibit current density–voltage (J–V) curves with obvious difference, especially in V_OC and fill factor (FF), as shown in Fig. 5d. The V_OC of the target bottom cell reaches 706 mV and is 25 mV higher than the control one, which may result from a 25 mV difference in iV_OC between the control and target p-type TOPCon structure as discussed in Fig. 1, as well as a 9 mV increase in iV_OC of the n-type TOPCon structure. It should be noted that the passivation difference between hydrogenated bottom cells and complete bottom cells may be explained by the unavoidable defects induced by plasma luminescence and electron or particle bombardment during ITO sputtering^40,41, increased recombination rate from the poly-Si metallization with metal^42,43,44, and H escape during ITO layer and metal electrode preparation^45,46,47. Additionally, the higher FF of the target bottom cell may also play a key role for increased efficiency. The lower contact resistivities of p- and n-type TOPCon structures in the target bottom cell lead to a lower series resistance of 0.6 Ω for the target bottom cell than 1 Ω for the control bottom cell, which may be the main reason for the higher FF. In summary, the optimized TOPCon structures yield both a higher V_OC and a higher FF, which endows the target bottom cell with a marginally increased efficiency. The statistical data of performance parameters of complete bottom cells can be found in Fig. S6.

n-i-p monolithic perovskite/silicon TSCs

After demonstrating the effectiveness of the improvements in p-type TOPCon structures and complete Si bottom cells, we fabricated n-i-p type monolithic perovskite/silicon TSCs using the target bottom cells (See Experimental Section for more details). The schematic view and cross-sectional SEM images of the TSCs are shown in Fig. 6a. Consequently, a champion efficiency of 28.20% with an V_OC of 1.90 V, a FF of 78.91% and a short-circuit current density (J_SC) of 18.82 mA·cm⁻² in 0.9226 cm² aperture area was obtained for the target device in our laboratory tests (Fig. 6b) which is the top-ranking level for n-i-p type monolithic perovskite/silicon TSCs at present. For n-i-p type monolithic perovskite/silicon tandem cells, Zheng et al. and Aydin et al. reported efficiencies of 27.2% and 27.1% for ~1 cm² tandem cells, respectively, which are the highest efficiencies for published n-i-p type monolithic perovskite/silicon tandem cells^48,49. The dominating reason for our higher efficiency is the higher V_OC, 1.9 V, compared to these two cells, 1.82–1.83 V. Another 1 cm² tandem cell reported by Shen et al. shows 24.5% efficiency, which is caused by a lower V_OC of 1.76 V and a J_SC of 17.8 mA·cm^−2 50. Therefore, our cell shows top-ranking efficiency for 1 cm² n-i-p type monolithic perovskite/silicon TSCs. Statistics of the photovoltaic parameters imply the improved performance and reproducibility with the target bottom cells (Fig. S7). Another tandem cell was sent to Shanghai Institute of Microsystem and Information Technology (SIMIT) for authoritative certification and achieved 27.31% (25.69%) efficiencies with over 1.91 V V_OCs in reverse (forward) voltage scanning directions (Fig. S8 and Table S3). The champion device from our lab measurements was not dispatched to SIMIT for calibration due to unavailability of testing schedules during that period. Regarding the comparison of results, the disparities observed in photovoltaic parameters such as V_OC, J_SC, FF, and PCE between our champion device in lab measurement and another device in SIMIT calibration are within the acceptable margin of <5%, which is commonly deemed satisfactory for devices sourced from different production batches. The notable variance between the two sets of testing results primarily stems from hysteresis, a phenomenon intricately linked to factors such as disparate bias scanning rates, pre-light soaking conditions, spectral distribution variations, ambient environmental disparities between the testing sites, and inherent differences in the devices themselves.

a Sketch structure (left) and cross-sectional SEM images (right) of the target tandem device. The scale bars are 500 nm. b J–V curves and (c) EQE spectra of the two related TSCs. d MPP tracking stability of TSCs with the control and target TOPCon bottom cells.

Full size image

Figure 6c exhibits the external quantum efficiencies (EQEs) and the integrated currents of the champion tandem devices. 0.26 and 0.66 mA·cm⁻² integrated current increases are unveiled for perovskite top cell and optimized silicon bottom cell, respectively, which is consistent with the J_SC from the J–V measurements. The increased current density in the target tandem cell, as observed from the EQE results, can be primarily attributed to the highly passivated p-type TOPCon structure achieved through our optimized process. Additionally, our optimized process results in an approximately 10 mV increase in the iV_OC of the rear-side n-type TOPCon structure, contributing to a slight improvement in the ~1000 nm wavelength zone of the EQE data. The current density of our tandem cell is limited by perovskite top cell, and the enhanced J_SC of J–V measurements for the target tandem device is consistent with the EQE results that exhibit ~0.2 mA cm⁻² improved integrated current density in the top cell. It should be noted that, the observed lower FFs in the complete bottom cell testing (73–75% for control and target cells) primarily stem from issues with the front metal gate-line. This results in lateral carrier transport loss within the ITO and p-type TOPCon structure during measurement, rather than inherent issues with the crystalline silicon bottom cell itself. However, this issue is alleviated in tandem devices, as carriers only need to recombine in the middle layer without encountering the challenges of lateral carrier transport and collection. In addition, the mismatch of current densities of top and bottom cells, which is 18.1–18.4 and 18.8–19.5 mA·cm⁻² respectively according to Fig. 6c, will also lead to higher FFs⁵¹. Consequently, while the complete bottom cell may exhibit relatively poor FFs, the corresponding tandem devices demonstrate higher FFs (ranging from 76% to 79%). Furthermore, maximum power point (MPP) tracking tests were conducted to monitor the operation stability of the un-encapsulated tandem devices under ~1 sun LED illumination (Fig. S9) in a N₂ flow. As shown in Fig. 6d, both types of the tandems demonstrate impressive longevities over 500 h, which indicates the commercialized potential of our tandem devices. The initial declines may originate from a “burn-in” decay often occurring in single-junction perovskite solar cells, which is related to ion migration, type of charge selective contact, and defect accumulation at the transport layer/perovskite interfaces^52,53,54,55.

In this work, a highly passivated p-type TOPCon structure on randomly textured industrial wafers was achieved using industry-compatible techniques, which leads to a high efficiency of an n-i-p type monolithic perovskite/Si TSCs. The enhanced thermal oxidation condition forms more uniform ultrathin SiO_x on textured silicon surface with higher Si⁴⁺ concentration and blue shift in BE, as well as lower interface state density at SiO_x/c-Si. This endows SiO_x with weaker distortion and lower recombination centers after high-temperature annealing, thus resulting in higher chemical passivation. The increased thermal budget of high-temperature annealing deepens boron in-diffusion, which promotes field-effect passivation soundly but Auger recombination slightly. Furthermore, a strengthened hydrogenation process was performed via increasing AlO_x:H thickness, passivating more defects and leaving fewer recombination centers a step further after hydrogen injection. As the consequence, the iV_OC of the p-type TOPCon structure increased to 715 mV, which is the summit passivation for the textured p-type TOPCon structure using ex-situ oxidation. Based on the optimized double-sided TOPCon bottom cell, the perovskite/Si TSCs exhibit a high V_OC of 1.9 V and a remarkable efficiency of 28.2%, which is the top-ranking level for n-i-p type monolithic perovskite/silicon TSCs currently.

Preparation and characterization of passivation samples

The crystalline silicon wafers used in this study were industrial n-type Czochralski (Cz) wafers with (100) oriental. The double-side textured wafers with ~155 μm thickness, ~0.8 Ω·cm resistivity, and pyramid size below 1 μm (sub-micrometer-size) (Fig. S10a) were prepared via an industrial texturing technique in the lab. The texturing process is performed in ~70 °C potassium hydroxide-contained aqua solution for ~15 min with 8 vol.% commercial sub-micrometer pyramid texturing additives under 800 rpm stirring. Such pyramid size was chosen for the convenience of the fabrication of perovskite top cell. After standard RCA cleaning, ultrathin silicon oxide layers were prepared via thermal oxidation on both sides of the wafers. The oxidation conditions were tuned in three dimensions, i.e., temperature (550–750 °C), duration time (1–9 min), and oxygen proportion (0–100%). Then, ~40 nm-thick boron-doped a-Si (p⁺ a-Si) was deposited on both sides of wafers using PECVD. The chamber temperature was 220 °C; SiH₄:H₂:B₂H₆ flow ratio was 5:20:3 sccm; pressure was 0.5 Torr; plasma power and deposition time was 5 W and 160 s, respectively. Afterwards, high temperature annealing was performed to facilitate silicon crystallization as well as boron diffusion and activation, which was followed by in situ wet nitrogen hydrogenation⁵⁶. The borosilicate glass (BSG) films above poly-Si were removed by dipping in diluted HF solution. Additional hydrogenation process was performed via AlO_x:H deposition in an ALD system, followed by vacuum annealing in a tube furnace. The ALD camber temperature was 200 °C; the pressure was 0.03 Torr; the pulse time for Trimethylaluminium/N₂/H₂O/N₂ is 0.15/10/0.2/10 s; the cycle number for 15 and 30 nm AlO_x:H was 115 and 230, respectively. At last, the chamber was purged with N₂ for 3 times. Finally, SiN_x coatings were deposited on both sides of the wafer by PECVD.

The passivation properties of planar and textured samples were characterized by the iV_OC, the single-side J_0,s and the τ_eff, which were obtained by Sinton WCT-120 lifetime tester^57,58,59. The former one was measured using quasi steady state (QSS) mode, and the latter two used transient mode. The contact resistivity of the optimized sample with a single-sided p-type TOPCon structure on a textured surface was measured referring the Cox-Strack method³⁹. Active boron concentration profiles in poly-Si and c-Si were measured based on the ECV method by WEP Wafer Profiler CVP21^60,61. Nano- or micro-structures of samples were observed by SEM using Hitachi Regulus 8230.

The characterizations of ultrathin SiO_x layer and SiO_x/c-Si interface include the thickness, integrity, and chemical state of SiO_x layer, and the residual D_it of SiO_x/c-Si interface. The SiO_x was prepared on polished (111)-oriented wafers for SE on Woollam Complete EASE equipment, and on textured wafers for TEM observation on Talos F200X. The measurements of chemical state of SiO_x and D_it of SiO_x/c-Si were performed toward the structure of SiO_x above textured wafers, via XPS on Axis Ultra DLD and C–V method²⁵ on Keysight B1500A, respectively. The H content in AlO_x:H film was represented by the integrated area of O-H bond peak, which was measured via FTIR on THermo NICOLET 6700.

Fabrication and test of TOPCon bottom cells

The c-Si bottom cells with double-sided TOPCon structures were prepared based on double-side textured n-type Cz (100)-oriental wafers with low bulk resistivity. These wafers were the same with those for passivation property. The bottom cell for tandem cell fabrication has a 2.5 × 2.5 cm² wafer size and 1 × 1 cm² work area, while the one for checking bottom cell performance has a 4 × 4 cm² wafer size and 2.2 × 2.2 cm² work area. Initially, SiN_x protection layer was deposited on the textured surface of a single-sided industrially textured wafer (Fig. S10b), which was followed by the texturing process to form a textured surface with pyramid size below 1 μm. Then, the SiN_x protection layer was removed by dipping in diluted HF solution. For the convenience of top cell fabrication, the side with a pyramid size below 1 μm was defined as the front side, while another side with industrial large pyramids was the rear side. After RCA cleaning, ultrathin silicon oxide layers were formed via thermal oxidation under optimized condition on both sides of wafers. Then, p⁺ a-Si and phosphorus-doped a-Si (n⁺ a-Si) were deposited on the front and rear side, respectively, by in situ PECVD. The deposition detail of p-type a-SiH₄ was the same with the passivation samples above. For n-type a-Si:H, the chamber temperature was 220 °C; SiH₄:H₂:PH₃ flow ratio was 5:20:6 sccm; pressure was 0.5 Torr; plasma power and deposition time was 6 W and 320 s, respectively. The following processes were high-temperature annealing, wet nitrogen hydrogenation, AlO_x hydrogenation, and SiN_x deposition, which were similar to symmetric passivation samples. The iV_OC and τ_eff were measured by Sinton WCT-120 lifetime tester^57,58,59. Then, SiN_x/AlO_x stack above the work area was removed by HF dipping. After that, ~10 nm-thick ITO was deposited on the front side as intermediate layer for the 2.5 cm wafer, but ~100 nm-thick ITO as a carrier collection layer for 4 cm wafer. The ITO film was prepared by physical vapor deposition. The passivation dropped drastically after ITO preparation, but it was recovered by forming gas annealing at 250 °C for 10 min. Afterwards, the work area on the rear side was fully covered by a ~ 100 nm-thick Ag metal electrode prepared by thermal evaporation. Here, an additional process was applied on the 4 cm wafer to form a stack of Al/Ag metal electrode with a grid and fingers above the ITO film using evaporation through a shadow mask. The passivation of the cell sample was monitored by photo-luminescence after AlO_x hydrogenation and subsequent steps. The performance of the bottom cells, including V_OC, J_SC, FF and efficiency, was tested by a 4-wire solar cell tester consisting of a Keithley 2400 source meter and a Class AAA solar simulator produced by EnliTech Co., Ltd, which provided a light intensity of 100 mW·cm⁻².

Fabrication and test of perovskite/silicon TSCs

To fabricate perovskite/silicon TSCs, a 12 nm-thick tin dioxide (SnO₂) layer were deposited on the top of silicon bottom cells by a 150-cycle thermal ALD (KE-MICRO, PE ALD-F50R) with the chamber at 120 °C and Tetrakis(dimethylamino)tin(IV) (TDMASn) source at 80 °C. TDMASn/purge1/H₂O/purge2 times were 0.4/5/1.5/15 s with a constant 90-sccm nitrogen flow. After UV-ozone treatment of the ALD-SnO₂ layer, a SnO₂ nanocrystal solution (Alfa Aesar, 15%) diluted ten times with a mixed deionized water and ethanol (1:1, vol:vol) was dynamically spin-coated on the first SnO₂ layer at 5000 rpm for 35 s. Then, 150 °C-30 min post-annealing and 15 min UV-ozone treatment were conducted. A 1.7 M Cs_0.05FA_0.8MA_0.15Pb(I_0.75Br_0.25)₃ perovskite precursor solution, fully dissolved into a mixed solvent system comprising anhydrous dimethylformamide/dimethyl sulfoxide (4:1, vol:vol), was then spin-coated at 600/2000/8000 rpm for 6/54/15 s, and 300 μL chlorobenzene as an anti-solvent was dropped onto the center of the substrate 10 s before the end of the rotation procedure. The perovskite absorber layer was annealed at 105 °C for 15 min. A 5 mg·mL⁻¹ phenethylammonium iodide (PEAI) in isopropanol was dynamically spin-coated on the perovskite upper surface at 5000 rpm for 35 s. 2,2′,7,7′-tetra(N,N-di-tolyl)amino-9,9-spiro-bifluorene (Spiro-TTB) doped with 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ) as the hole transport layer was thermally evaporated to a 20 nm thickness with a ~ 14.3 wt.% doping ratio. For the front transparent electrode, 15 nm-thick molybdenum oxide (MoO_x) and 100 nm-thick indium zinc oxide (IZO) were deposited by thermal evaporation at a 0.2 Å·s⁻¹ rate and radio frequency sputtering under a 45 W power, respectively. Silver was evaporated through a shadow mask to a 300 nm thickness with a 1 × 1 cm² active area. Finally, a 100 nm-thick magnesium fluoride (MgF_x) was thermally evaporated as the antireflection layer.

The cross-sectional SEM images of TSCs were collected using a field-emission SEM (S-4800, Hitachi). The J–V measurements were performed through a digital source meter (Keithley 2400) and a solar simulator (94022 A, Newport) with illumination calibrated by a standard silicon cell (Bunkoukeiki, BS-520BK). The curves were achieved both in reverse (2.0 to −0.1 V) and forward (−0.1 to 2.0 V) voltage scanning modes with 200 data points. The mask for J–V measurements has a 0.9226 cm² aperture area calibrated by SIMIT. EQE measurements were carried out through a QE system (QEX10, PV measurement, Inc). For perovskite top cell measurement, an infrared light-bias LED with 850 nm peak emission was used to saturate the silicon bottom cells, and a 0.6 V bias voltage was used to build almost short-circuit conditions. For silicon bottom cell measurement, a blue light-bias LED with a 455 nm peak emission was used to saturate the perovskite top cells and a 1 V bias voltage was applied to build an almost short circuit condition. For MPP tracking of tandems, the un-encapsulated devices operated under ~1 Sun LED illumination in a N₂ flow at room temperature. The illumination intensity was calibrated to 100 mW·cm^-2 with the standard silicon cell from J–V measurements.

Reporting Summary

Further information on research design is available in the Nature Research Reporting Summary linked to this article.